On Jun 23, 7:41 am, "ALu...@[EMAIL PROTECTED]
" <ALu...@[EMAIL PROTECTED]
> wrote:
> Hi,
>
> I am using the following globally static expression:
>
> CASE ((InputAddressRegisterReg(13 DOWNTO 1) & '0') AND
> cREGADDRGeneralRangeMask) IS
> ....
>
> When trying to compile that VHDL module with Modelsim I get the error
> message:
> Error: f:/sim/sim_msd/../../Src/Src_rtl/ProcInterface/
> ProcInterface.vhd(930): (vcom-1014) Array type case expression must be
> of a locally static subtype.
>
> When putting it to synthesis with Synplify it is no problem at all.
> Hardware is working fine.
> So how can I solve that simulation "mismatch" ?
>
> Rgds
> Andre
Assign a variable with that expression, and use the variable in the
case statement.
Because the language defines the case statement as requiring mutually
exclusive and exhaustive choices, the compiler has to "know" the size
of your expression in the case statement, at compile time. The "and"
function return type is an unconstrained vector, and is defined in a
package, so the compiler does not know how wide the vector is when it
compiles this file, so the compiler cannot guarantee mutual exclusive
and exhaustive choices. Putting it in a container (variable) that is
known solves the problem.
The synthesis tool (synplify) should not accept the code either; enter
a bug re****t.
Andy
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