Sorry, I thought the complete topic would be posted.
Here is the original one: (comp.arch.fpga)
I have designed a VHDL single clock FIFO with write pointer that can
either be confirmed or cleared
that is the read side of the fifo does see the write counters only
when these have been confirmed
by the write side. One application can be the confirmation of a
packet
including a checksum at the end. If the checksum is not correct the
whole packet is not released to the read side of the FIFO.
Confirmation and
clearing of the write pointer does also work while read pointer is in
progress (that is reading a packet received
and confirmed before).
Now I want to implement the same mechanism for dual clock fifo. As a
starting point I am using the Xilinx paper
"xapp131.pdf" to build a dual clock fifo. What is your opinion about
integrating that write pointer confirm / clear
mechanism into the Xilinx module ? Where do you see pitfalls on
confirming / clearing the write pointer on dual clock fifo?
Thank you for your opinion.
Rgds
Andre
