I think Mike pointed out all the problems, I thought Id now just get a
little picky with the code :)
You are using clock'event and clk = 1, for your rising edge triggers.
VHDL93 adds two functions "rising_edge(clk)" and "falling_edge(clk)"
that function exactly the same but I think make the code a little more
readable.
> write_ram: process(clk,rst, we)
> begin
> if (clk'event and clk ='1') then
You only need to put "clk" in the sensitivity list here, because
output only change on clock events. In a large design, this may slow a
simulation down as it is triggering processes unnessarily.
>rst_gen: process
> begin
> wait for 30 ns;
> rst <= '0';
> end process rst_gen;
In this process, rst is being assigned to '0' every 30ns. This will
probably not cause a problem, but it does make "rst'transaction" go
high for that single delta. Personally, I would put "wait;" after "rst
<= '0';" to halt the process;
|
