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Electronic Equipment > VHDL > Re: new to vhdl
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Re: new to vhdl

by Vandana <nairvan@[EMAIL PROTECTED] > Jun 27, 2008 at 06:27 AM

On Jun 27, 7:52 am, KJ <kkjenni...@[EMAIL PROTECTED]
> wrote:
> On Jun 27, 4:12 am, Tricky <Trickyh...@[EMAIL PROTECTED]
> wrote:
>
>
>
> > >rst_gen: process
> > >  begin
> > >       wait for 30 ns;
> > >      rst <= '0';
> > >  end process rst_gen;
>
> > In this process, rst is being assigned to '0' every 30ns. This will
> > probably not cause a problem, but it does make "rst'transaction" go
> > high for that single delta. Personally, I would put "wait;" after "rst
>
> Or simply...
>
> rst <= '1', '0' after 30 ns;
>
> KJ


@[EMAIL PROTECTED]
 I initialized the ram array, then I was able to get rid of the
undefined values. The waveforms look better, but I doubt if
the array initialization is synthesizable.
Thanks for pointing out to your code snippets, they will be of help.

@[EMAIL PROTECTED]
 @[EMAIL PROTECTED]
 I actually intended to use the wait to halt the process
not to make rst go high after every 30 ns. Thanks for pointing it
out.

Thanks,
Vandana
 




 5 Posts in Topic:
new to vhdl
Vandana <nairvan@[EMAI  2008-06-26 08:53:14 
Re: new to vhdl
Mike Treseler <mike_tr  2008-06-26 10:58:11 
Re: new to vhdl
Tricky <Trickyhead@[EM  2008-06-27 01:12:12 
Re: new to vhdl
KJ <kkjennings@[EMAIL   2008-06-27 04:52:07 
Re: new to vhdl
Vandana <nairvan@[EMAI  2008-06-27 06:27:34 

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tan12V112 Mon Dec 1 16:04:26 CST 2008.