can anyone tell me what's wrong with this assert statements. hereis my code: ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 17:54:42 05/12/2008 -- Design Name: -- Module Name: fifoashani - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity fifo is ****t( wren : in std_logic; rden: in std_logic; reset : in std_logic; clk : in std_logic; data : in std_logic_vector(3 downto 0); stackfull: out std_logic; stackempty: out std_logic; dop: out std_logic_vector(3 downto 0)); end fifo; architecture Behavioral of fifo is type stack is array(0 to 7) of std_logic_vector(3 downto 0); signal int_reg : std_logic_vector(3 downto 0); signal int_stack : stack; signal countup: integer :=0; signal countdn: integer :=0; signal stackempty_var: std_logic :='0'; signal stackfull_var : std_logic :='0'; begin process(clk) begin if(clk'event and clk='1') then if (reset = '1') then stackfull_var <= '0'; stackempty_var <= '0'; countup <= 0; countdn <= 0; int_reg <= "0000"; elsif(wren = '1') then assert not (countup>7) re****t " stackfull" severity NOTE ; -- if(countup>7) then -- stackfull_var <='1'; int_stack(countup)<= data; countup <= countup + 1; elsif(rden = '1') then assert (countdn >7) re****t "stack empty" severity NOTE ; -- if(countdn > 7) then -- stackempty_var <= '1'; int_reg <= int_stack(countdn); countdn <= countdn + 1; end if; end if; end process; dop <= int_reg; stackfull <= stackfull_var; stackempty <= stackempty_var; end Behavioral;