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Latest 200 Posts:
| Post Title | Post by | Date |
| Analog Cell Library Design | nicollete <newbie... | Oct 13, 2008 at 01:35 PM |
| Re: ERC Checking tools | spyder <nowgimmea... | Aug 27, 2008 at 07:56 AM |
| ERC Checking tools | spyder <nowgimmea... | Aug 27, 2008 at 07:54 AM |
| SPAM | robert bristow-johns... | Aug 14, 2008 at 08:20 PM |
| Re: comp.dsp name | julius <juliusk@[... | Aug 14, 2008 at 04:26 PM |
| HSPICE | harikrishna <hari... | Aug 11, 2008 at 10:39 AM |
| BDD-package CUDD | Monika <Monika.Ge... | Jul 10, 2008 at 02:50 AM |
| CAD tools for SOI chip design | Avinash <avinash_... | Jul 10, 2008 at 02:35 AM |
| Re: WereEveryWhere.net | "N:dlzc D:aol T... | May 25, 2008 at 10:52 AM |
| BDD package for teaching on WINDOWS | a2003zz <a2003zz@... | Apr 20, 2008 at 11:02 AM |
| ISCAS Benchmark information | marc <lilo2@[EMAI... | Apr 18, 2008 at 03:56 AM |
| Error during Spice simulation | "Pegasus" ... | Mar 31, 2008 at 10:53 AM |
| Re: Unsuccessful Simulation | Paul <no@[EMAIL P... | Mar 29, 2008 at 12:37 PM |
| Unsuccessful Simulation | ecnedad <ecnedad@... | Mar 28, 2008 at 07:45 AM |
| FPGA/CPLD group on LinkedIn | wmwmurray@[EMAIL PRO... | Mar 8, 2008 at 06:07 AM |
| Extraction from Simulation Result | ecnedad <ecnedad@... | Mar 2, 2008 at 04:49 AM |
| Physical Design Opportunities for Mindtree | "anitha_have@[E... | Jan 31, 2008 at 11:19 PM |
| writing dc_shell-t output | mmb9305 <michelle... | Jan 29, 2008 at 08:13 AM |
| CFP: DATICS 2008 - Design, Analysis and Tools for ... | ss.datics@[EMAIL PRO... | Jan 23, 2008 at 02:09 PM |
| Check This Out!!! | nanyangrose@[EMAIL P... | Jan 15, 2008 at 10:52 PM |
| Repeatedly call of SKILL function | psalms_17@[EMAIL PRO... | Jan 10, 2008 at 02:32 PM |
| Scholarships for PhD study in Informatics@Edinburg... | Don Sannella <D.T... | Dec 31, 2007 at 03:20 PM |
| Final call for papers - ISQED08 | "SVTI" <... | Oct 28, 2007 at 11:25 AM |
| Re: I Strangled My Dog Then Fucked it | none <""... | Oct 21, 2007 at 09:05 AM |
| Youtube Video Downloader KEYGEN 9968 [2/2] | vvudby@[EMAIL PROTEC... | Oct 19, 2007 at 11:49 PM |
| IEEE ISQED08 FINAL CALL FOR PAPERS | "SVTI" <... | Oct 16, 2007 at 10:27 AM |
| Re: Logic minimization software with LUT6 support? | "comp.arch.fpga... | Sep 27, 2007 at 08:21 AM |
| Re: Logic minimization software with LUT6 support? | Ray Andraka <ray@... | Sep 26, 2007 at 07:57 PM |
| Re: Logic minimization software with LUT6 support? | "John_H" &... | Sep 26, 2007 at 04:46 PM |
| Re: Logic minimization software with LUT6 support? | Ray Andraka <ray@... | Sep 26, 2007 at 07:42 PM |
| Re: Logic minimization software with LUT6 support? | dudesinmexico@[EMAIL... | Sep 26, 2007 at 04:29 PM |
| Re: Logic minimization software with LUT6 support? | Ray Andraka <ray@... | Sep 26, 2007 at 06:57 PM |
| Re: Logic minimization software with LUT6 support? | hal-usenet@[EMAIL PR... | Sep 26, 2007 at 05:26 PM |
| Re: Logic minimization software with LUT6 support? | dudesinmexico@[EMAIL... | Sep 26, 2007 at 03:20 PM |
| Re: Logic minimization software with LUT6 support? | "comp.arch.fpga... | Sep 26, 2007 at 02:24 PM |
| Re: Logic minimization software with LUT6 support? | Marc Randolph <mr... | Sep 26, 2007 at 03:48 AM |
| Logic minimization software with LUT6 support? | dudesinmexico@[EMAIL... | Sep 25, 2007 at 02:30 PM |
| where I can get the eqntott program? | candydaria@[EMAIL PR... | Sep 21, 2007 at 10:44 AM |
| MEBES format | achaisemartin@[EMAIL... | Sep 20, 2007 at 09:58 AM |
| ISQED08 Call for Papers | "ISQED" &l... | Sep 9, 2007 at 02:26 PM |
| Re: flow of PD | Svenn Are Bjerkem &l... | Aug 23, 2007 at 10:25 AM |
| flow of PD | "," <tm... | Aug 21, 2007 at 06:11 AM |
| SynaptiCAD AllProducts, Synopsys, new programs, | ola7 <springsingr... | Jul 19, 2007 at 01:13 AM |
| Re: Where is Klaas Holwerd's GDSII viewer? | google@[EMAIL PROTEC... | Jul 4, 2007 at 12:19 AM |
| Re: Where is Klaas Holwerd's GDSII viewer? | Svenn Are Bjerkem &l... | Jun 29, 2007 at 01:48 PM |
| Where is Klaas Holwerd's GDSII viewer? | google@[EMAIL PROTEC... | Jun 28, 2007 at 12:49 PM |
| Free Structural Design Software | "Ingenieur Netw... | May 28, 2007 at 03:17 PM |
| Re: interconnect simulation | Svenn Are Bjerkem &l... | Apr 24, 2007 at 01:54 PM |
| GUI for SIS | Michele Russo <ru... | Mar 16, 2007 at 07:48 PM |
| Re: a problem when using dc_shell-t>report_lib | "Alvin Andries&... | Feb 25, 2007 at 11:02 PM |
| Linux and cygwin version of espresso | Ed Beroset <beros... | Feb 25, 2007 at 05:24 PM |
| interconnect simulation | "mina" <... | Feb 24, 2007 at 12:42 AM |
| a problem when using dc_shell-t>report_lib | "hurricane"... | Feb 21, 2007 at 08:47 AM |
| Magma EDA tool help | "Ruddha" &... | Feb 21, 2007 at 12:18 AM |
| Studentships for PhD study in Informatics@Edinburg... | Don Sannella <D.T... | Dec 22, 2006 at 03:47 PM |
| SAIF parser for download? | aranjan@[EMAIL PROTE... | Nov 27, 2006 at 02:32 AM |
| Graph Data structure to storing components in spic... | "Jonay Aloat&qu... | Nov 23, 2006 at 06:11 PM |
| Help on Ledit | "punnu" &l... | Nov 2, 2006 at 12:43 AM |
| UMC to TSMC process help! | "John" <... | Oct 26, 2006 at 06:13 PM |
| Magic Hspice extraction | kartheeharan@[EMAIL ... | Oct 15, 2006 at 12:27 PM |
| CFP: EvoHOT 2007 | squillero@[EMAIL PRO... | Sep 28, 2006 at 10:52 AM |
| hi everyone .measure problem tspice | "Bijoy" &l... | Sep 27, 2006 at 08:01 PM |
| Calculate Delay from .Lib file | "Ali Arabi"... | Aug 28, 2006 at 04:41 PM |
| default case synthesis (Espresso BLIF) | vnwarrior@[EMAIL PRO... | Aug 26, 2006 at 06:16 AM |
| Call for Papers - IEEE ISQED07 | "ISQED" &l... | Aug 16, 2006 at 10:39 PM |
| Tango PCB+ For Sale | singlewchildren@[EMA... | Jul 5, 2006 at 10:03 PM |
| Re: IBM's AET2 all events trace version 2 format ? | "Del Cecchi&quo... | Jun 2, 2006 at 09:28 PM |
| Re: IBM's AET2 all events trace version 2 format ? | mk<kal*@[EMAIL PR... | May 31, 2006 at 08:30 AM |
| how to generate CLOCKDR signal from TAP controller... | huzaifa.ginwalla@[EM... | May 19, 2006 at 04:53 PM |
| gds viewing problem in electric | "fox34" &l... | May 15, 2006 at 06:29 AM |
| computer bus technology discuss community | "benjamin.disra... | May 11, 2006 at 06:11 AM |
| Re: IBM's AET2 all events trace version 2 format ? | "acd" <... | May 3, 2006 at 01:38 AM |
| IBM's AET2 all events trace version 2 format ? | mk<kal*@[EMAIL PR... | May 3, 2006 at 07:42 AM |
| oceanEval statement in monte carlo simulation in s... | zhanyuanjiang@[EMAIL... | Apr 5, 2006 at 07:06 PM |
| Help Required.. Tanner TSpice Simulator giving a f... | swetap@[EMAIL PROTEC... | Apr 4, 2006 at 10:22 PM |
| hi | "soumya" &... | Apr 4, 2006 at 10:09 PM |
| two professional technology forums | water9580@[EMAIL PRO... | Mar 29, 2006 at 08:09 AM |
| SIS | diogenes.barrel@[EMA... | Mar 23, 2006 at 11:58 PM |
| OPC Rules | "szamani" ... | Mar 18, 2006 at 06:44 AM |
| Can Primetime work without constraints? | "Fazela" &... | Mar 16, 2006 at 01:45 PM |
| Sell quickturn production of printed circuit board... | njsldz@[EMAIL PROTEC... | Feb 16, 2006 at 11:58 PM |
| ISQED'06 CFP | "ISQED" &l... | Feb 17, 2006 at 03:28 AM |
| Advanced DRC software for $3K | "llc" <... | Feb 8, 2006 at 04:18 PM |
| Re: Study material for logic design | "Salah" &l... | Jan 11, 2006 at 09:06 AM |
| Re: Study material for logic design | "Fazela" &... | Jan 11, 2006 at 04:39 AM |
| Study material for logic design | salah.kazi@[EMAIL PR... | Jan 8, 2006 at 08:35 PM |
| Latest CAD forums messages on your desktop | google@[EMAIL PROTEC... | Dec 25, 2005 at 01:35 PM |
| Validating Tetramax Patterns | "Fazela" &... | Dec 19, 2005 at 08:08 AM |
| Studentships for PhD study in Informatics@Edinburg... | "Don Sannella&q... | Dec 18, 2005 at 06:01 PM |
| editing 2nd rank cells in LASI | bobrics@[EMAIL PROTE... | Nov 29, 2005 at 01:31 PM |
| Looking for Scott Davidson | "Fazela" &... | Nov 22, 2005 at 07:54 PM |
| Modeling memories in Liberty. | aranjan@[EMAIL PROTE... | Nov 17, 2005 at 12:10 AM |
| CFP EvoHOT'06 (**DEADLINE EXTENSION**) | "Dr. Giovanni S... | Oct 31, 2005 at 03:53 AM |
| HSPICE .tr0 file | wolfchild02@[EMAIL P... | Oct 29, 2005 at 04:06 PM |
| Re: HSpice Simulation | "Gerry Vandeval... | Oct 18, 2005 at 05:20 PM |
| HSpice Simulation | nkharan@[EMAIL PROTE... | Oct 17, 2005 at 07:06 AM |
| 3.0.3 release of stabie-soft layout editor | stabie@[EMAIL PROTEC... | Sep 11, 2005 at 09:52 AM |
| Re: Verilog Reference: Thomas & Moorby book | glen herrmannsfeldt ... | Sep 9, 2005 at 03:38 PM |
| for farrand: genuinely interesting nntp server acc... | brody <amprnet@[E... | Sep 6, 2005 at 11:55 PM |
| Free DataSheet Site........ | "DataSheet"... | Aug 28, 2005 at 11:34 PM |
| MEBES translator | stabie@[EMAIL PROTEC... | Aug 20, 2005 at 12:38 PM |
| GDS backup's on 9 Tracks | cvendel@[EMAIL PROTE... | Jul 26, 2005 at 09:48 AM |
| Re: HSPICE model parameter passing | Jim Thompson <the... | Jul 26, 2005 at 07:26 AM |
| HSPICE model parameter passing | "Subhajit"... | Jul 26, 2005 at 05:53 AM |
| Accessing TDX | cvendel@[EMAIL PROTE... | Jul 16, 2005 at 09:08 PM |
| Books: Verilog and VHDL | "hdl_book_selle... | Jun 19, 2005 at 06:16 PM |
| Re: module compiler ? | "Alvin Andries&... | Jun 15, 2005 at 09:43 PM |
| spice3 Fedora x64 graphics problems | Cecil Aswell <c4j... | Jun 10, 2005 at 06:29 AM |
| WORK FROM HOME..EARN THOUSANDS INVEST only 100 | "Hari Narayanan... | May 16, 2005 at 10:13 PM |
| Static Free Electric | "Pat" <... | Apr 21, 2005 at 06:22 AM |
| New Stabie-Soft release | stabie@[EMAIL PROTEC... | Apr 19, 2005 at 07:48 AM |
| Re: Searching for Kevin Brace (Graphic chip resear... | "Derek Simmons&... | Mar 31, 2005 at 01:51 AM |
| Analog/Mixed-Signal ASIC Designer for contract in ... | fallot@[EMAIL PROTEC... | Mar 27, 2005 at 01:52 AM |
| Re: How to Rename a sheet in ViewDraw (DxDesigner ... | Stuart Brorson <s... | Mar 23, 2005 at 12:13 PM |
| How to Rename a sheet in ViewDraw (DxDesigner 2.0)... | mohit82@[EMAIL PROTE... | Mar 22, 2005 at 08:23 PM |
| Re: Good Verilog & VHDL reference books | "Amontec, Larry... | Mar 21, 2005 at 11:48 PM |
| Good Verilog & VHDL reference books | "hdl_book_selle... | Mar 21, 2005 at 08:11 AM |
| Searching for Kevin Brace (Graphic chip research i... | "Derek Simmons&... | Mar 21, 2005 at 06:33 AM |
| Help on Looser-Take-All / Winner-Take-All circuit | etantonio@[EMAIL PRO... | Mar 15, 2005 at 07:51 AM |
| Free version of Rincon Harmonic Balance simulator ... | "gserdyuk"... | Mar 15, 2005 at 02:08 AM |
| Re: module compiler ? | "P Ruetz" ... | Mar 14, 2005 at 01:27 AM |
| Re: how to compile spice3 for ms-dos | mk<kal*@[EMAIL PR... | Mar 12, 2005 at 10:52 AM |
| how to compile spice3 for ms-dos | chungpingw@[EMAIL PR... | Mar 12, 2005 at 12:56 AM |
| module compiler ? | mk<kal*@[EMAIL PR... | Mar 11, 2005 at 10:02 PM |
| Summer Internship wanted. | "serious_chap&q... | Feb 18, 2005 at 05:31 PM |
| matt parker alias anjaparker@yahoo.com | mattparker@[EMAIL PR... | Jan 28, 2005 at 03:41 AM |
| Stabie-Soft releases version 3 of its layout softw... | stabie@[EMAIL PROTEC... | Jan 19, 2005 at 09:38 AM |
| Q: GnuCap output in binary | T R Gowrishankar <... | Jan 13, 2005 at 11:00 AM |
| ASK VIA http://cam.to/crack-cad/ CRACKED SOLIDWORK... | postcard@[EMAIL PROT... | Jan 9, 2005 at 08:47 AM |
| Electronics Software, CAX EDA and Other Design, ot... | "tel" <... | Jan 8, 2005 at 11:26 PM |
| Studentships for PhD study in Informatics@Edinburg... | Don Sannella <dts... | Dec 20, 2004 at 05:30 PM |
| Sample and hold or switched capacitor noise simula... | matthewlawrencecohen... | Dec 16, 2004 at 12:17 PM |
| No traffic? | "Bjørn B. Larse... | Dec 7, 2004 at 10:12 AM |
| New book: SystemVerilog Assertions Handbook | hdlcohen@[EMAIL PROT... | Dec 1, 2004 at 10:18 AM |
| Books, books, books: best reference texts for Veri... | hdl_book_seller@[EMA... | Nov 30, 2004 at 06:26 PM |
| Bulk Email Lists | Yelena Assing <Ye... | Nov 29, 2004 at 02:11 PM |
| Winter School on Timing for Deep Submicron Chips, ... | mark_josephs_outgoin... | Nov 23, 2004 at 06:50 PM |
| Re: Outputting DC inductor current in HSPICE | malleablecandy@[EMAI... | Nov 19, 2004 at 10:51 AM |
| Re: dram circuits | dale@[EMAIL PROTECTE... | Nov 18, 2004 at 09:45 PM |
| Re: Outputting DC inductor current in HSPICE | "Bjørn B. Larse... | Nov 19, 2004 at 09:03 AM |
| changing the vt of a nmos model | ausaaf@[EMAIL PROTEC... | Nov 18, 2004 at 06:50 PM |
| Outputting DC inductor current in HSPICE | malleablecandy@[EMAI... | Nov 18, 2004 at 04:28 PM |
| Empty Space Evaluator | zuandachein@[EMAIL P... | Nov 17, 2004 at 06:00 PM |
| Re: dram circuits | johnjakson@[EMAIL PR... | Nov 17, 2004 at 07:30 AM |
| Re: dram circuits | johnjakson@[EMAIL PR... | Nov 13, 2004 at 08:33 AM |
| Re: dram circuits | "Bjørn B. Larse... | Nov 12, 2004 at 03:48 PM |
| Re: dram circuits | Marcus Schaemann <... | Nov 10, 2004 at 02:00 PM |
| Re: dram circuits | glen herrmannsfeldt ... | Nov 9, 2004 at 04:20 PM |
| dram circuits | adnan_aziz@[EMAIL PR... | Nov 9, 2004 at 02:50 PM |
| comparator problem | yshashi@[EMAIL PROTE... | Nov 3, 2004 at 11:09 AM |
| ANSOFT HFSS V9.2, DESIGNER V1.1, PEXPRT V5.0, ANSO... | code_fu@[EMAIL PROTE... | Oct 5, 2004 at 03:51 AM |
| Ansoft Designer v2.0 - I'm finding a copy, despera... | "News su Libero... | Oct 5, 2004 at 06:12 AM |
| International Symposium on Visual Computing (ISVC0... | bebis@[EMAIL PROTECT... | Oct 1, 2004 at 02:47 PM |
| Sample or training for MSC Superforge | "EXPAND Dev&quo... | Sep 22, 2004 at 09:14 AM |
| IAR visualSTATE v5.0.7.88, IAR Embedded.Workbench ... | vvcd@[EMAIL PROTECTE... | Sep 21, 2004 at 05:34 PM |
| Automation Studio - Circuit Design and Simulation ... | zorba@[EMAIL PROTECT... | Sep 16, 2004 at 12:24 PM |
| IEEE ICM'2004 last Call For Papers | Kholdoun TORKI <K... | Sep 4, 2004 at 04:32 PM |
| Stabie-Soft announces point to point router | stabie@[EMAIL PROTEC... | Sep 3, 2004 at 06:56 AM |
| Serenade for win98 | "Alfred Lorona&... | Aug 21, 2004 at 10:56 PM |
| IEEE Extended Call For Papers ICM'2004 | Kholdoun TORKI <K... | Aug 17, 2004 at 03:05 PM |
| Design Methodology Head (Bangalore, India) | marcelle@[EMAIL PROT... | Aug 13, 2004 at 02:56 AM |
| spice models | kubik <jackgroups... | Aug 8, 2004 at 01:17 PM |
| Call for Papers: ASYNC-2005 (New York City) | noreply--nospam--@[E... | Jul 29, 2004 at 05:23 PM |
| updated errata for book *Algorithms for VLSI Desig... | Sabih Gerez <sabi... | Jul 4, 2004 at 01:46 AM |
| MEBES format | thuong_u@[EMAIL PROT... | Jul 2, 2004 at 05:06 PM |
| a5n0a | jihadbomb@[EMAIL PRO... | Jun 20, 2004 at 03:58 AM |
| charges n766n | jihadbomb@[EMAIL PRO... | Jun 20, 2004 at 01:10 AM |
| comp.sys.mac.oop.powerplant,misc.transport.rail.mi... | nocker@[EMAIL PROTEC... | Jun 19, 2004 at 03:32 AM |
| nqjzn | jihadbomb@[EMAIL PRO... | Jun 19, 2004 at 03:30 AM |
| Synthesis question | linjiah@[EMAIL PROTE... | Jun 19, 2004 at 03:13 AM |
| eqntott package | yunzhang73@[EMAIL PR... | Jun 17, 2004 at 03:10 PM |
| Summer Internships At SciEssence | "David Rivkin, ... | May 31, 2004 at 12:17 AM |
| Bangalore-based SoC Wireless Design Manager | jbires@[EMAIL PROTEC... | May 26, 2004 at 01:57 PM |
| Bangalore-based ASIC/CAD Tech Lead, Parasitic Extr... | jbires@[EMAIL PROTEC... | May 26, 2004 at 01:56 PM |
| Re: Simple way to generate random netlists of ALU ... | Fred Ma <fma@[EMA... | May 18, 2004 at 08:07 AM |
| Re: Simple way to generate random netlists of ALU ... | Ray Andraka <ray@... | May 17, 2004 at 09:57 PM |
| Re: Simple way to generate random netlists of ALU ... | Fred Ma <fma@[EMA... | May 15, 2004 at 01:18 PM |
| Re: Simple way to generate random netlists of ALU ... | johnjakson@[EMAIL PR... | May 15, 2004 at 05:07 AM |
| MCNC benchmarks (was: Simple way to generate rando... | Fred Ma <fma@[EMA... | May 15, 2004 at 10:55 AM |
| Re: Simple way to generate random netlists of ALU ... | Fred Ma <fma@[EMA... | May 15, 2004 at 02:58 AM |
| Re: Simple way to generate random netlists of ALU ... | Fred Ma <fma@[EMA... | May 15, 2004 at 02:47 AM |
| Re: Simple way to generate random netlists of ALU ... | Ray Andraka <ray@... | May 14, 2004 at 07:51 PM |
| Announce. Open Source Harmonic Balance Simulator | gserdyuk@[EMAIL PROT... | May 14, 2004 at 04:29 PM |
| Re: Simple way to generate random netlists of ALU ... | Fred Ma <fma@[EMA... | May 14, 2004 at 09:58 PM |
| Re: Simple way to generate random netlists of ALU ... | johnjakson@[EMAIL PR... | May 14, 2004 at 06:25 AM |
| Simple way to generate random netlists of ALU cell... | Fred Ma <fma@[EMA... | May 14, 2004 at 06:00 AM |
| Physical Design Engineer Req in Bangalore | "Gangatharan&qu... | May 1, 2004 at 05:44 PM |
| Verilog RTL of a Galois Field Multiplier | rajesh_99@[EMAIL PRO... | Apr 23, 2004 at 08:51 AM |
| Verilog RTL of a Galois Field Multiplier | rajesh_99@[EMAIL PRO... | Apr 23, 2004 at 08:50 AM |
| Re: Issues on a Clockless UART | "Bjørn B. Larse... | Apr 22, 2004 at 09:30 AM |
| Issues on a Clockless UART | shashi22k@[EMAIL PRO... | Apr 21, 2004 at 12:46 PM |
| ///NEWEST CAD/CAM/CAE PROGRAMS\\\ | David Wiliss <019... | Mar 28, 2004 at 11:59 PM |
| Re: EDA CAD | "hondo" &l... | Mar 28, 2004 at 09:07 AM |
| Does somebody has the program Crouzet ? | "Wim Bongaerts&... | Mar 22, 2004 at 05:25 PM |
| Jurassic CAD | "Francesco Quar... | Mar 20, 2004 at 08:06 AM |
| EDA CAD | jhmorris47@[EMAIL PR... | Mar 15, 2004 at 06:38 AM |
| Using Pspice | sub_sen@[EMAIL PROTE... | Mar 15, 2004 at 03:01 AM |
| Job Opening available Immediately | Ravi Poddar <ravi... | Mar 12, 2004 at 04:52 PM |
| Mentor ADK and Leonardo without enread | Mike Dyer <m.dyer... | Mar 10, 2004 at 02:47 PM |
| Candidate looking for job | "The Lord of Ch... | Mar 9, 2004 at 02:43 PM |
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