I am synthesizing using dc_shell-t and would like to write out the
resulting netlist so I can perform place and route and post-PAR
simulations using Xilinx ISE. I have been able to write out the
resulting VHDL file with the following command:
write -format vhdl -hier -out mapped/testFUB.vhd
However, there are constructs used within this file that are not
defined in the testFUB.vhd file that was outputted in the previous
command. I imagine that these components are defined in the library I
am referencing in my dc_shell-t setup file, but I am unable to output
this database file (ext. is ".db") as a file that Xilinx ISE can
understand. As a result, I am unable to do simulations because there
are undefinded components being used.
Can someone help?
