I'm in the preliminary stages of designing an ASIC that has
2,147,450,880 memory locations. Each memory location contains 256
bits of a score value. Bus A, for data coming out of the memory loca-
tions, and Bus B, for data coming into the memory locations, connect
each memory location to the central processor. The central processor
can broadcast an address of one of the memory locations on Bus B, and
thus read the contents of that memory location on Bus A.
But the central processor needs to also be able to broadcast a
score value on Bus B, and the memory locations need to be set up so
that each location with a score less than or equal to the broadcast
score writes its address to Bus A.
The problem here is that there might be more than one memory lo-
cation with score less than or equal to the broadcast score, which
would have more than one memory location writing to Bus A at the same
time.
I'm trying to find a way for the central processor to be able to
detect a rough measure of how many memory locations are writing to Bus
A at one time. In particular, I want it to be able to tell whether
the number of memory locations writing to it are zero, one, or more
than one. I'm thinking that in addition to the several bits for data
that make up Bus A, I want to have one line set up so that if a memory
location is writing a value to Bus A, then that memory location sends
a current onto that line. I want the resistance on that line to in-
crease roughly pro****tionately to the current, not so much that the
current stays constant, but enough to keep the current from getting
dangerously high if, for example, _every_ memory location is sending a
current to this line. And then, when the central processor checks the
current on this line it can tell whether that current indicates that
zero, one, or more than one memory location is writing to that line.
Is such a circuit possible? It's kind of a digital-analog hy-
brid, with three relevant values instead of just two. And instead of
voltage being the quantity that determines the value of the circuit,
it's the current. (Or could I still use the voltage? If resistance
increases as the current increases, then the voltage would go down,
right? So could I tell from the voltage level whether zero, one, or
more than one memory location is writing to the line?) This determi-
nation, distingui****ng between those three conditions, would have to
be fairly fast, hopefully within one clock cycle. Is that a possibi-
lity? If not, how many clock cycles would it _take_ to distinguish
between those three conditions?
My background is in Computer Science, not VLSI. Would I need to
take some cl***** in Electrical Engineering or Computer Engineering to
be able to answer this question? Any information on this would be
greatly appreciated.
---Kevin Simonson
"You'll never get to heaven, or even to LA, if you don't believe
there's a way."
from _Why Not_
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