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Electronic Equipment > LSI > TLB implementat...
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TLB implementation: CAM vs SRAM

by adnan.aziz@[EMAIL PROTECTED] Nov 9, 2005 at 09:46 AM

i was curious as to why TLBs are implemented using CAMs.

specifically, it seems to me that the organization used in caches
(e.g., 4-way set associative) would work as well for a TLB as for a
D-cache - you can make much larger SRAMs than CAMs.

i'm guessing it has something to do with the fact that the page table
already gets the benefit of the cache, but it's not obvious.  (maybe a
small CAM is faster than the cache?)

cheers,
adnan

ps - i teach a CMOS vlsi design class at UT Austin, and we're covering
RAMs, which led to this question
 




 8 Posts in Topic:
TLB implementation: CAM vs SRAM
adnan.aziz@[EMAIL PROTECT  2005-11-09 09:46:47 
Re: TLB implementation: CAM vs SRAM
"Iain McClatchie&quo  2005-11-09 11:01:09 
Re: TLB implementation: CAM vs SRAM
"Dale Morris" &  2005-11-09 20:36:33 
Re: TLB implementation: CAM vs SRAM
MitchAlsup@[EMAIL PROTECT  2005-11-09 12:41:28 
Re: TLB implementation: CAM vs SRAM
"robertwessel2@[EMAI  2005-11-09 14:27:58 
Re: TLB implementation: CAM vs SRAM
Dysthymicdolt@[EMAIL PROT  2005-11-11 10:44:31 
Re: TLB implementation: CAM vs SRAM
adnan.aziz@[EMAIL PROTECT  2005-11-16 10:09:38 
Re: TLB implementation: CAM vs SRAM
"Dale Morris" &  2005-11-21 15:46:24 

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