TLB implementation: CAM vs SRAM

i was curious as to why TLBs are implemented using CAMs.

specifically, it seems to me that the organization used in caches
(e.g., 4-way set associative) would work as well for a TLB as for a
D-cache - you can make much larger SRAMs than CAMs.

i'm guessing it has something to do with the fact that the page table
already gets the benefit of the cache, but it's not obvious.  (maybe a
small CAM is faster than the cache?)

cheers,
adnan

ps - i teach a CMOS vlsi design class at UT Austin, and we're covering
RAMs, which led to this question