hi everyone,
i'm teaching a vlsi design class, and we're covering datapath this
week.
we use weste and harris' new edition of "cmos vlsi design". it's a
great book; however, it doesn't discuss actual delays/area costs for
adders, multipliers, dividers, etc., and the other sources i've looked
at tend to be focused on asymptotics (O(log N) type analyses).
does anyone know off the top of their heads what the actual delay/area
numbers are like on a modern processor for the following:
addition, multiplication, division
16/32/64 bit
number of pipeline stages for these implementations.
i'd also be interested in knowing correspondnig values for floating
point arithmetic, and for FPGA implementations.
suggestions for survey articles would be welcome (i know i could just
skim the JSSC for the past several years, but it's unlikely that i'll
be able to do that before the end of cl*****).
thanks in advance,
adnan
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