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Re: AMD Phenom L3 cache bug explained

by Ed <nospam@[EMAIL PROTECTED] > Dec 6, 2007 at 08:12 PM

On Thu, 06 Dec 2007 03:51:42 -0500, Yousuf Khan <bbbl67@[EMAIL PROTECTED]
>
wrote:


>Also I saw a roadmap today from AMD which talks about a "Large L3 cache" 
>coming in 2008. That may be Z-RAM. Separately, there was even a rumour 
>that any Z-RAM cache could be upto 100MB!!!
>
>Check page 30 of this PDF, where the roadmap stuff starts:
>http://www.cisl.ucar.edu/dir/CAS2K7/Presentations/torricelli.pdf

At AMD's last analyst day meeting there was no mention of Z-Ram that I
can recall. That pdf is old.

They claimed the first AMD64 K8s were capable of 8MB L2 caches but they
never did more then 1MB per core, probably because of yields, die size,
and the performance gains just weren't noticeable enough, their
architecture just doesn't seem to benefit much from larger caches, even
the new chips with L3 cache don't appear to be making any big impact.

Ed
 




 11 Posts in Topic:
AMD Phenom L3 cache bug explained
Yousuf Khan <bbbl67@[E  2007-12-05 14:17:24 
Re: AMD Phenom L3 cache bug explained
Ed <nospam@[EMAIL PROT  2007-12-06 00:35:47 
Re: AMD Phenom L3 cache bug explained
Yousuf Khan <bbbl67@[E  2007-12-06 03:51:42 
Re: AMD Phenom L3 cache bug explained
Ed <nospam@[EMAIL PROT  2007-12-06 20:12:10 
Re: AMD Phenom L3 cache bug explained
Yousuf Khan <bbbl67@[E  2007-12-07 18:11:56 
Re: AMD Phenom L3 cache bug explained
Robert Myers <rbmyersu  2007-12-06 13:37:02 
Re: AMD Phenom L3 cache bug explained
Jan Panteltje <pNaonSt  2007-12-06 22:01:53 
Re: AMD Phenom L3 cache bug explained
Yousuf Khan <bbbl67@[E  2007-12-07 16:36:49 
Re: AMD Phenom L3 cache bug explained
Jan Panteltje <pNaonSt  2007-12-07 22:10:19 
Re: AMD Phenom L3 cache bug explained
Yousuf Khan <bbbl67@[E  2007-12-07 18:05:22 
Re: AMD Phenom L3 cache bug explained
Robert Myers <rbmyersu  2007-12-07 17:05:04 

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