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Re: Rambus aims for 1 TeraByte per second memory bandwidth by 2010

by daytripper <day_trippr@[EMAIL PROTECTED] > Dec 7, 2007 at 05:51 PM

On Fri, 7 Dec 2007 12:49:09 -0800 (PST), Robert Myers
<rbmyersusa@[EMAIL PROTECTED]
>
wrote:

>On Dec 7, 9:47 am, Robert Redelmeier <red...@[EMAIL PROTECTED]
> wrote:
>> In comp.sys.ibm.pc.hardware.chips Robert Myers <rbmyers...@[EMAIL PROTECTED]
>
wrote in part:
>>
>> > On Dec 5, 12:31 am, daytripper <day_tri...@[EMAIL PROTECTED]
> wrote
>> >> Of course, the first question they had was "what about latency?"
>>
>> > Bandwidth is king.  Said it long ago.  Wider is the only
>>
>> Uhm, err, for what sorts of problems/tasks?  Had bandwidth
>> been always and overall governing, Rambus first iteration
>> would have succeeded.  Their execs obviously thought they
>> had technical advantages worth the commercial conditions.
>> The market disagreed.
>>
>Rambus was hot and expensive.
>
>To turn your argument over, if latency were king, Intel would be out
>of business and/or have changed tactics drastically.  Intel has taken
>its own sweet time about moving away from its traditional memory
>architecture and seems to be doing quite nicely.
>
>> > way left to go.  We will see more and more of same and the
>> > only thing to do about latency is to hide it.
>>
>> This has often been tried with only partial success (video)
>> Sometimes latency governs and cannot be hidden (databases).
>> It must be reduced as AMD has done fairly successfully.
>>
>That's a one-time gain that has been known to be available at least
>since the last editions of alpha.  For latency, there is nowhere left
>to go in terms of completely unpredictable reads from memory (or
>disk).  All the tactics that work (prefetch, hide, cache) depend on
>the ability to foresee the future, another hobby horse of mine.  Terje
>might claim that improvements come from cache management.
>Improvements in cache management come from more successfully
>exploiting nonrandomness; that is to say, the ability to predict the
>future.
>
>Robert.

So, in short, you don't think the biggest problem confronting processor
design
and performance isn't im****tant because "it's hard"...

/daytripper (well, that's one way to go, I guess ;-)
 




 12 Posts in Topic:
Re: Rambus aims for 1 TeraByte per second memory bandwidth by 20
daytripper <day_trippr  2007-12-04 00:48:29 
Re: Rambus aims for 1 TeraByte per second memory bandwidth by 20
Terje Mathisen <terje.  2007-12-04 08:03:36 
Re: Rambus aims for 1 TeraByte per second memory bandwidth by 20
"Chris Thomasson&quo  2007-12-03 23:17:43 
Re: Rambus aims for 1 TeraByte per second memory bandwidth by 20
"Del Cecchi" &l  2007-12-04 16:11:14 
Re: Rambus aims for 1 TeraByte per second memory bandwidth by 20
daytripper <day_trippr  2007-12-05 00:31:25 
Re: Rambus aims for 1 TeraByte per second memory bandwidth by 20
a?n?g?e?l@[EMAIL PROTECTE  2007-12-06 05:03:43 
Re: Rambus aims for 1 TeraByte per second memory bandwidth by 20
Robert Redelmeier <red  2007-12-07 14:47:39 
Re: Rambus aims for 1 TeraByte per second memory bandwidth by 20
daytripper <day_trippr  2007-12-07 17:51:06 
Re: Rambus aims for 1 TeraByte per second memory bandwidth by 20
"Ken Hagan" <  2007-12-10 10:31:39 
Re: Rambus aims for 1 TeraByte per second memory bandwidth by 20
John Ahlstrom <Ahlstro  2007-12-10 14:37:43 
Re: Rambus aims for 1 TeraByte per second memory bandwidth by 20
Robert Redelmeier <red  2007-12-08 07:18:08 
Re: Rambus aims for 1 TeraByte per second memory bandwidth by 20
Robert Redelmeier <red  2007-12-11 15:19:00 

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