Re: Clarifications about AMD TLB L3 bug

On Dec 14, 4:02 pm, Yousuf Khan <bbb...@[EMAIL PROTECTED]
> wrote:
> Robert Myers wrote:
> > A number of assertions have been made here about the AMD TLB L3 Bug:
>
> > 1. Only affects virtualization.
>
> > 2. Is fixed in 64-bit Linux without a significant performance hit.
>
> > 1. TRUTH: AMD, which knew about the bug before the chip was released,
> > falsely made this claim.  The bug apparently affects all workloads,
> > potentially resulting in a system freeze.
>
> The truth actually is that it only affects virtualized workloads,
> because the problem occurs when nested page tables are used. Nested page
> tables only are used in virtualization, no other times. AMD never made
> the claim it only affects virtualization, it is actually trying to keep
> that hushed up: I assume because it does not want a virtualization bug
> to be associated with its products since that kind of a reputation would
> be hard to shake off, even if fixed.

It's not clear to me whether that is true or not.  Here's the bug:

"The processor operation to change the accessed or dirty bits of a
page translation table entry in the L2 from 0b to 1b may not be
atomic. A small window of time exists where other cached operations
may cause the stale page translation table entry to be installed in
the L3 before the modified copy is returned to the L2. In addition, if
a probe for this cache line occurs during this window of time, the
processor may not set the accessed or dirty bit and may corrupt data
for an unrelated cached operation. The system may experience a machine
check event re****ting an L3 protocol error has occurred. In this case,
the MC4 status register (MSR 0000_0410) will be equal to
B2000000_000B0C0F or BA000000_000B0C0F. The MC4 address register (MSR
0000_0412) will be equal to 26h."

I know what a Page Table Entry is, but I'm not sure what a PTTE
is...it sort of sounds like the nested page table.  Perhaps someone
who is intimately familiar with the architecture could comment?

> > 2. TRUTH: A fix is available under NDA for RHEL 4 and not otherwise
> > apparently.
>
> >http://techre****t.com/discussions.x/13721
>
> >http://techre****t.com/discussions.x/13724
>
> How secret can it be if it's open-source?

Really easy, nobody cares enough to sue AMD/RH to get it.  It's not
like there are more than 10-20 end users for Barcelona at the moment.

DK