Re: Multi-core and memory

On May 21, 10:12=A0am, Evandro Menezes <evan...@[EMAIL PROTECTED]
> wrote:
> On May 20, 5:15 pm, MitchAlsup <MitchAl...@[EMAIL PROTECTED]
> wrote:
>
> > Opteron with its on-chip DRAM controller and on-board chip-to-chip
> > interconnect has had multiple memory controllers for (=BFwhat?) 4.5
> > years now.....
>
> Actually, K8 had a dual-channel controller, meaning that it would keep
> track of RAM resources for both channels, such as open pages, etc.
> For example, if a RAM page was open, it was open on both channels.

Yes, the later K8s did (rev =BFC? and above).
Although generally marketed as "allowing more 'stuffings' of the DRAM
arrays" it was, in effect two DRAM controllers hiding behind 1 memory
controller.

> With Barcelona though does have two independent controllers. =A0For
> example, a RAM page on one "channel" might not have a corresponding
> open page on the other "channel".

Barcelona is an enhancement of the later K8 dual controllers, with a
much greater write buffer depth and a watermarked write back scheme,
and a much more clever DRAM scheduling scheme. Some prefetching is
done by the DRAM controller itself on cycles that are not otherwise
"in demand". Something that CPU-based and Cache-based prefetchers
cannot do--because they cannot figure out when the cycles are free.

The decision to run the DRAM banks as one channel of 128 bits (Plus
ECC as desired) or as two channels of 64-bits is done at boot time. If
all the DRAMs on both channels can comply with the same timings,
simulations showed that generally the 1 channel twice as wide
performed better. When a random mix of DRAM timings is "stuffed" into
the sockets, the controler manages both banks independently with the
slowest timings on that bank. You particular BIOS may allow you to run
the DRAMs as 2 banks even if all the timings are the same.

Mitch