Re: Multi-core and memory

"MitchAlsup" <MitchAlsup@[EMAIL PROTECTED]
> wrote in message 
news:f308699c-58e3-4cb9-b5b6-72f4ed79c1d7@[EMAIL PROTECTED]
 May 22, 12:23 am, "Chris Thomasson" <cris...@[EMAIL PROTECTED]
> wrote:
[...]
> > IMVHO, drastically reducing the physical distance between the chip and

> > its
> > local memory can be very im****tant factor wrt scalability concerns. It
> > should be ideal to merge the chip and a couple of GB of memory into a 
> > single
> > unit.
> >
> > Intra-CPU to local memory communication would use shared memory, and
> > inter-CPU and remote memory communication would use message passing.
It
> > seems the scheme could be made to work... What am I missing?

> Heat disipation. One could, in principle, design a DRAM daughtercard
> that had an Opteron/Barcelona socket in the middle, ranks of DRAMs to
> the left and right, and HT links through the pins. Dealing with the
> 100Watts of power at the center would make the spacing between
> daughter cards pretty large, and cooling a little on the difficult
> side.

> BUT it is possible today, if you wanted to try and make a go of it.

Humm. I was thinking that a clever mixture of high-end liquid cooling 
systems and fans might be able to help things out in this specific problem

domain.