On Sep 1, 12:01=A0pm, Robert Redelmeier <red...@[EMAIL PROTECTED]
> wrote:
> Robert Myers <rbmyers...@[EMAIL PROTECTED]
> wrote in part:
>
> > Your constant harping on a single figure of merit is beyond tiresome.
>
> ??? you must have me confused with someone else. =A0I do _NOT_
> claim that latency is the only or even the most im****tant
> factor in computing. =A0However, I do say latency is sometimes
> a critical factor and should receive attention.
>
You're not the worst, if that's what you mean by having you confused
with someone else.
> > For the thousandth time, my problems tend to be memory bound.
>
> Yours may well be. =A0I try to look beyond the bounds of my
> immediate experience and consider what others needs might be.
>
It's unlikely that you're in a position to do that. Intel may be
clueless about users, but they pretty generally get to talk to
everyone about their problems. I'm sure that AMD does, too. Terje,
whom you later quote, has consulted to Intel. Terje has his own
obsessions.
The conversation in this and similar forums is sometimes hard to take,
as if the poster had some exquisite knowledge that (say) Intel was
just too thick to fathom. That's just plain crazy on the face of it.
I'd *love* to be on the inside of Intel. Not because I'm all that
interested in the weenie details of how transistors are arranged, but
by how such a large organization assimilates information about
conflicting needs and copes with it.
It doesn't really matter whether I can see the entire landscape of
computing clearly or not. Good thing, because I can't, and neither
can you.
> > As to using older architectures, that's
> > clearly happening, because the modern developments don't
> > really help in some situations, like transaction servers.
>
> Precisely my point. =A0I do not understand the DDR2 bus signals
> well enough to know whether it could tolerate SRAM devices
> (even with proper glue) and their short latency. =A0Such a
> development of drop-in "super-premium" memory modules would
> bypass the huge hurdle of new MMUs, mobos and RAM stds.
>
If you want to have a thread about that, why not start a thread? If
you want to talk about physics and electrical engineering and not
personalities, I'll be happy to participate.
> > It's your focus on a single aspect of a very
> > complicated problem that just makes me crazy. =A0
>
> You flatter me. I do not believe I have that power.
>
To make me crazy? You've been doing a pretty good job here.
> > For the most part, we've driven right up to that wall and
> > through it without mussing a hair. =A0It's a crazy way to
> > live, but it is the way we are living: through fakery and
> > bulltet-dodgin, not through brute force hardware design.
>
> Well, I still suggest PC performance has become unbalanced
> and may increasingly limited by this imbalance. =A0Over the
> past decade, CPU speeds have increased by ~15x, bandwidth by
> 10-16x, avg RAM by ~100x, yet latency by 2x at most.
>
> Your predictability/prefetch solution has also weakened as cache
> sizes have also not increased much. =A0Especially L1 (prefetch dest)
> while expansions in L2 have also usually resulted in slowdowns.
> This becomes even more glaring as a ratio of memory/problem size.
>
All true, except that it's not my predictability/prefetch soluution.
> > One final thought. =A0The predictability problem is everywhere
> > in computing. =A0You can call it the latency problem if you
> > wish, but you're always stuck trying to anticipate.
>
> "almost all programing can be viewed as an exercise in caching"
> Terje Mathison 1994.
>
I know Terje. He's smart. Smarter than his one-liner would suggest.
Robert.
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