Robert Myers <rbmyersusa@[EMAIL PROTECTED]
> wrote in part:
> On Sep 1, 12:01 pm, Robert Redelmeier <red...@[EMAIL PROTECTED]
> wrote:
>> I try to look beyond the bounds of my immediate
>> experience and consider what others needs might be.
> It's unlikely that you're in a position to do that.
I don't claim omniscience, but I certainly am in a position to
_try_ to see beyond my cir***stances. Everyone is. And should.
> I'd *love* to be on the inside of Intel. Not because I'm all
> that interested in the weenie details of how transistors are
> arranged, but by how such a large organization assimilates
> information about conflicting needs and copes with it.
Having spent considerable time inside a large multinational,
my experience is that conflicting needs/info are resolved by
internal champions. An individual/dept takes a position,
often to their (budget, personnel) benefit, sometimes
only for prestige. Then pushes it through the heirarchy.
Rarely is there direct conflicting opposition but frequently
there are competing claims of higher priorities.
> It doesn't really matter whether I can see the entire
> landscape of computing clearly or not. Good thing, because
> I can't, and neither can you.
I did not claim to be able to do so. I merely claim it is
im****tant to try. Attitude towards knowledge is frequently
more im****tant than the knowledge itself.
>> I do not understand the DDR2 bus signals well enough to
>> know whether it could tolerate SRAM devices (even with
>> proper glue) and their short latency. Such a development
>> of drop-in "super-premium" memory modules would bypass
>> the huge hurdle of new MMUs, mobos and RAM stds.
> If you want to have a thread about that, why not start a thread?
Because that is not where it arose. It arose in composing a
response here and is directly germaine to my latency position.
If you think it worthwhile, nothing stops you from elevating
your response to a new thread.
> If you want to talk about physics and electrical engineering
> and not personalities, I'll be happy to participate.
I have not seen evidence of this. You have repeatedly ignored
technical data in this thread and instead responded personally.
The easiest way to have a technical discussion is to say nothing
else. Let data make your case.
>> > It's your focus on a single aspect of a very complicated
>> > problem that just makes me crazy.
>> You flatter me. I do not believe I have that power.
> To make me crazy? You've been doing a pretty good job here.
I assure you that such is not my aim. If you find yourself
distressed, I earnestly suggest you seek advice from your
mental health practictioner.
>> Your predictability/prefetch solution has also weakened as
>> cache sizes have also not increased much. Especially L1
>> (prefetch dest) while expansions in L2 have also usually
>> resulted in slowdowns. This becomes even more glaring as
>> a ratio of memory/problem size.
> All true, except that it's not my predictability/prefetch soluution.
You were advocating it, so in that conversational sense it becomes
yours. I do not believe you created it, nor are claiming credit.
>> "almost all programing can be viewed as an exercise in
>> caching" Terje Mathison 1994.
> I know Terje. He's smart. Smarter than his one-liner would suggest.
That quote is actually very clever, with many layers of meaning.
-- Robert
|
