Re: tiny inductor with every bypass cap?

"Talal Itani" <titani@[EMAIL PROTECTED]
> wrote in message 
news:suk7k.3904$JL.2049@[EMAIL PROTECTED]
> >
>> To be honest 50uH and 0.1uF is a recipe for disaster. At the most a 
>> ferrite SMT-bead should be used but usually I don't even do that. A
nice 
>> full ground plane and a nice full VCC plane is usually best. Problem
with 
>> DSP like this is that you need an additional lower voltage supply so
now 
>> you are up to three supply planes, meaning you won't get away with less

>> than a 6-layer board.
>>
>> If it's super critical you could have the analog supplies come from a 
>> separate regulator but often converters on a chip with fast digital 
>> processing going on are quite disappointing. A bond wire affords only
so 
>> much in RF conductivity.
>>
>> Hint: Carefully read up on power supply sequencing. Best case wriobng 
>> sequencing leads to a locked up DSP, worst case to a dead DSP.
>>
>> Oh, and please don't top post.
>>
>
> This DSP has 3.3V and 1.8V supply voltages.  Can the same plane have
both 
> voltages?

Talal,

You really need some consulting help if you're asking questions like this.

The edge rates of your signals are likely to be very fast, and this
requires 
some real know-how when it comes to designing the circuitry, clock 
distribution and trace lengths, and the general pcb layout. The previous 
comment regarding supply sequencing should be heeded, too.

A short answer for you is this:

If you can arrange it, the controlled-impedance traces should couple to
(be 
adjacent to) solid (unsplit) GND plane layers. Then, you can split your 
supply planes as you need. Otherwise, you have to be very careful in
routing 
your traces so as to avoid coupling gaps which will result in large 
high-inductance coupling loops, or add extra decoupling to couple these 
split planes near their splits.

You should seek some professional help for your design and/or take a class

in high-speed signal integrity.

Bob
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