Re: tiny inductor with every bypass cap?

"MK" <nospam@[EMAIL PROTECTED]
> wrote in message
news:pfudnXEZ-P7tzcLVnZ2dnUVZ8umdnZ2d@[EMAIL PROTECTED]
>
> "Vladimir Vassilevsky" <antispam_bogus@[EMAIL PROTECTED]
> wrote in message
> news:8vA7k.5248$L_.3435@[EMAIL PROTECTED]
> >
> >
> > MK wrote:
> >
> >> I designed a board with an 'F2808 about 2 years ago.  Based on TI app
> >> notes I
> >> put 100nH in series with the two ADC power pins only and 2uF to
ground
on
> >> each (2 * 0603 caps - different values).
> >>
> >> Was it necessary - I don't know - never tried it without.
> >>
> >> Did the ADC work - yes - I was impressed at how well it worked.
> >
> > The internal ADC of TI 28xx is crap. It has tremendously inacurate
> > internal reference and high zero offset. With 12 bits available, the
true
> > accuracy is about 8 bits unless you have the ADC calibrated.
> >
> >> The board was 4 layers with careful design of gorund planes/fills
around
> >> the processor and decoupling caps on both sides.
> >
> > There is no need for 4 layer board with 28xx. The layout can be done
on
> > two layers just fine. Been there, done that.
> >
>
> We were able to arrange for calibration of the ADC on board and could
easily
> deal with the offset issues.
>
> We went 4 layer because we wanted it to work first time, 6M samples/sec
and
> reasonable ADC performance for an on chip quite fast ADC.
> It worked and was delivered on time and to spec.

> Sure we could have got it on 2 layers, delivered it late, not quite
working
> and saved a few £ on the board.
>
> Did you never hear of "good, cheap, quick - pick any two" ?
>

We develop the consumer applications where every $ matters. Two vs four
layer PCB is a big difference in the cost, so I don't use the multilayer
boards unless it is really required. Despite of the popular beliefs, many
analog or digital designs can be built in two layers just fine. It takes
care, understanding and attention to details.

I averaged several sequential conversions of the 28xx ADC to get better
noise performance, so I traded the speed for the SNR. It worked like
expected for the noise however the problem was the beat tones between the
ADC clock and the peripheral clock. Had to optimize the division ratios.
The
ADC manual is pretty vague (as it is usual with TI), so it is not clear
what
is the exact position of the sampling instants of the sequencer, and how
the
whole thing works. What set me off is that there are two similar but not
quite the same sequencers there. Another stupid thing is that the ADC
range
is 0...3V absolute, not 0...3.3V ratiometric. So the 3.3V can't be used as
the reference for the level ****fting, etc. unless the 3.3V is measured
against the internal reference.


Vladimir Vassilevsky
DSP and Mixed Signal Consultant
www.abvolt.com