Re: Flash retention in uC at higher temps, experience?

On Sat, 14 Jun 2008 09:14:57 -0700, Joerg
<notthisjoergsch@[EMAIL PROTECTED]
> wrote:

>Paul Keinanen wrote:
>> On Fri, 13 Jun 2008 16:58:25 -0700, Joerg
>> <notthisjoergsch@[EMAIL PROTECTED]
> wrote:
>> 
>>> One could add some code so it re-flashes itself once in a while,
that's 
>>> another option here. However, the device cannot lose power during that

>>> brief period or it'll be really toast. So that would require large 
>>> enough electrolytics and some pre-regulator voltage monitoring. The 
>>> latter would require a relayout, bigger ECO and all that. Not a VP of 
>>> Engineering's favorite path, usually.
>> 
>> In a high radiation environment usually some ECC bits are stored in
>> each sector and with frequent sector reads you can detect if there are
>> flipped bits, correct the errors using the ECC and write back the
>> sector.
>> 
>> In this way, you know when to do the writeback and you can minimize
>> the (limited) number of refla****ng for a specific sector on the flash.
>> 
>> I assume this would also work with the data retention time problem at
>> elevated temperatures.
>> 
>> For a program written in assembly, it should not be a problem to
>> allocate a number of bytes for the ECC bits at the end of sector and
>> use a branch instruction to skip them, but this might be an issue, if
>> an HLL is used.
>> 
>
>That's an option as well. Although it won't help with power failure 
>duyring re-writes.

With sector specific ECC, you reduce the likelihood for sector
specific refla****ng and also reduce the time of reflash (full
reflash/sector specific reflash). 

If this kind of reducing the likelihood for a complete failure is not
sufficient e.g. large capacitors for data retention, you have to go
for a doubly/triple redundant system to avoid such problems.

Paul