Talk About Network

Google


Register and Login
Nick
Password
Register create new account Sign up is FREE and you can post replies, new topics, bookmark posts and more!
Recover lost password


Electronic Equipment > Engineering Semiconductors > How will passiv...
Latest [ Topics | Posts ] Archive Post A New Topic Post a Reply
<< Topic < Post Post 1 of 2 Topic 749 of 805
Post > Topic >>

How will passivation anneal affect the device leakage current

by Jim Chim <chimwaikwong@[EMAIL PROTECTED] > Feb 19, 2008 at 01:46 AM

I performed the below experiment and got the below results about
passivation anneal and leakage current.

1) Conditions: Passivation anneal + Polyimide + Polyimide cure
Results: Good NMOS and PMOS transistor leakage, around 1pA/um.

2) Conditions: Passivation anneal, no Polyimide, no Polyimide cure
Results: Poor NMOS and PMOS transistor leakage, around 100pA/um.

3) Conditions: Passivation anneal + Polyimide cure
Results: Good NMOS leakage (1pA/um), but sometimes high PMOS
transistor leakage, around 10pA/um.

I think the Polyimide cure helps to improve device leakage.  However,
I don't understand
1) Why in experiment 3, NMOS is good while PMOS is bad sometimes.

Many thanks if anyone can share with me his/her experience.
 




 2 Posts in Topic:
How will passivation anneal affect the device leakage current
Jim Chim <chimwaikwong  2008-02-19 01:46:07 
Re: How will passivation anneal affect the device leakage curren
jason0class@[EMAIL PROTEC  2008-02-25 00:52:44 

Post A Reply:
  Go here to Signup

AddThis Feed Button


About - Advertising - Contact - Frequently Asked Questions - Privacy Policy - Terms of Use - Signup

Contact
tan12V112 Fri Nov 21 14:36:34 CST 2008.